The logic analyzer is an analytical instrument for analyzing the relationship of digital logic. The signal to be measured is judged by a comparator. If the reference voltage is higher than the reference voltage, the lower than the reference voltage is Low, and a digital waveform is formed between High and Low. What is the specific purpose of the logic analyzer? The following is a small series to introduce the function of the logic analyzer, I hope to help everyone.
Logic analyzer function
Timing analysis
The timing analyzer is the oscilloscope-like part of the logic analyzer. It is the same way that the oscilloscope displays information. The horizontal axis represents time and the vertical axis represents voltage amplitude. The timing analyzer first samples the input waveform and then uses a user-defined voltage threshold to determine the high and low levels of the signal. The timing analyzer can only determine if the waveform is high or low and there is no intermediate level. So the timing analyzer is like a digital oscilloscope with only 1 bit vertical resolution. However, the timing analyzer cannot be used to test parameters. If you use timing analysis to measure the rise time of the signal, then you are using the wrong instrument. If you want to check the timing relationship of signals on several lines, the timing analyzer is a reasonable choice. If the signal sampled by the timing analyzer is a state, and the signal sampled this time is another state, then it knows that the input signal has jumped at some point between the two samples, but the timing analysis The instrument does not know the exact moment. In the worst case, the uncertainty is a sampling period.
Jump timing
If we want to sample and save data for a long time without change, the hopping timing can make efficient use of the memory. With hopping timing, the timing analysis only saves the samples acquired after the signal hopping, as well as the time of the last hop.
Burr capture
Glitching in digital systems is a headache. Some timing analyzers have glitch capture and triggering capabilities that make it easy to track unpredictable burrs. Timing analysis can effectively sample input data and track any transitions between samples to easily identify glitch. In timing analysis, the glitch is defined as any transition between samples that traverses the logic threshold multiple times. Displaying glitch is a useful feature that helps to determine the cause of the glitch by triggering the glitch and displaying the data before the glitch is generated.
State analysis
The state of the logic circuit is a sample of the bus or signal line sampled when the data is valid. The main difference between timing analysis and state analysis is that the timing analysis is controlled by the internal clock control, and the sampling and the system under test are asynchronous; the state analysis is controlled by the clock of the system under test, and the sampling is synchronized with the system under test. Use the timing analyzer to see when the event “when†occurs and use the status analyzer to check for “what†events. Timing analyzers typically display data in waveforms, and state analyzers typically display data in a list.
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